Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation

Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation

Jack H. Arabian

Index Terms — Optimization, Semiconductors, Production, Testing, Process, Mapping, Modeling, Simulation, System of Systems, Six Sigma, Estimation.

I. Introduction

Testing of Hardware and Product in the Semiconductor Production Process presented a challenge to the collection of data to resolve cost and production issues. As described in reference [1], it has been shown that the Process can be modeled and run with respect to maximizing the output of the model for typical parameters of cost, time, and resources.

It remained, however to optimize the human resources with respect to maximizing the output of the model. This paper describes an optimizing technique/tool, which can be used for a manufacturing test process identifying defects to predict/estimate and optimize costs, scheduling and needed resources.

II. Requirements

Given the model described in [1], the following steps were taken:

III. Procedure

optimizer converges on the best solution. Experiment 1 shows the best solution of Minimum quantity four (4) workers from the Worker Pool, and the Maximum NumberOfDice_1=1400.000 and Maximum

Number0fDice_2=1000.000, as shown in Fig. 4.

IV. Conclusion

Process Mapping and Dynamic Time Simulation is very useful for a manufacturing test process identifying defects to predict/estimate costs, scheduling and needed resources.

Reference [1] showed the previous outcome of metrics, and this paper shows how to optimize the human resources with the process output. This is another compelling argument for QA engineers to justify up-front costs of JTAG (Joint Test Action Group for boundary scan) or BIST (Built-in Self Test) circuitry in design phases.

In addition, there are other advantages to modeling a process, viz.

Manuscript received July 9, 2009. This work was supported by the Jacobs Engineering, Technology Division of Bedford, MA

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Fig. 1. Model of the Semiconductor Manufacturing and Testing Process

Fig. 2. SimRunner Table for Optimizer Inputs

Fig. 3. Plot of Objective Function vs. Simulator Runs (Experiments)

V. Live Demo

For this presentation, a 10-minute live demonstration of SimRunner™ optimizer shows dynamic, graphic animation of the test runs automatically generated until the optimizer’s Objective Function converges on the best solution

VI. Future Work

This model is generic to many manufacturing and test processes in which defects can occur, as, e.g., hardware defects found in testing on a manufacturing production line. Many other aspects need to be shown, such as importing of global parameters from a spreadsheet instead of tedious insertion of parameters in each step of a long process. Process mapping and dynamic time simulation will also lead to future work in creating a true System of Systems (SoS) model through the ability to connect multiple processes and raise levels of abstraction, which are otherwise not easy to achieve.

In conjunction with Quality Assurance and Six Sigma practices, other processes can be similarly treated such as in business (order process, Help desk), finance (transactions), healthcare (claims processing), aerospace (radar tracking, checklist, countdown, communications, command and control) and shipbuilding (welding, supply chain).

Acknowledgment

The author gratefully acknowledges the support and encouragement of the Jacobs Engineering, Technology Division of Bedford, MA

References

[1] Selected Cost Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation; IEEE Proceedings East-West Design and Test Symposium 2008, Lvov, Ukraine, September 2008. By Jack H. Arabian, Engineering Specialist, Jacobs Engineering Technology Division, Bedford, MA 01731

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Fig. 4. SimRunner Optimizer Converging on Best Solution

As founder of Comparative Management Associates, LLC Jack Arabian provides process mapping, modeling and simulation on a contract, consulting basis. He has trained many corporate groups on the topics of process improvement, process mapping and simulation, software and hardware defect detection and correction, engineering design and applications, manufacturing, finance.

His forthcoming book, Process Modeling Simulation for All Organizations, will be his fourth, including Computer Integrated Electronics Manufacturing and Testing, and Concurrent and Comparative Discrete Event Simulation, the standard references for manufacturing engineers and designers of automated factories.

In a distinguished career with such innovative companies as Westinghouse, Polaroid, Foxboro Company, and Digital Equipment Corporation, Jack led the design and development of highly successful hardware and software products in the aerospace systems industry. He has built, led, and mentored high performance design and engineering teams, and taken technology from the laboratory to the customer, with consistently high levels of success in terms of both product quality and profitability.

At the MIT Instrumentation Laboratory, Jack played a key leadership role in solving the problem of gyroscope drift in space navigation. The results proved critical to the success of the lunar landing program, including the safe return of Apollo 13 after a crippling explosion, and later to the development of commercial aircraft inertial navigation systems.

At both Foxboro Company and Polaroid, Jack developed innovative automated test equipment that allowed the restructuring of complex factory production lines, doubling both production and quality while decreasing time to market by as much as 30%.

While at Digital, Jack was instrumental in testing computers through modeling and simulation programs, a technique that developed a reputation and a book on the subject. This technique is now used to enhance and accelerate process development and reengineering.

A graduate of Harvard University (B.A., Engineering Sciences and Applied Physics) and Massachusetts Institute of Technology (M.S., Instrumentation), Jack has extensive global experience. He is proficient in five languages, including Armenian, Japanese, Spanish, and French.

In addition to his four books, Jack is the author of numerous papers on a wide variety of technical and managerial topics, a frequent after-dinner speaker, and a presenter at leading international conferences, such as the IEEE International Test Conference, and symposia.

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