Algebra-Logical Repair Method for FPGA Logic Blocks

Algebra-Logical Repair Method for FPGA Logic

Vladimir Hahanov, Eugenia Litvinova, Wajeb Gharibi, Olesya Guz

Abstract — An algebra-logical repair method for FPGA functional logic blocks on the basis of solving the coverage problem is proposed. It is focused on implementation into Infrastructure IP for system-on-a chip and system-in-package. A method is designed for providing the operability of FPGA blocks and digital system as a whole. It enables to obtain exact and optimal solution associated with the minimum number of spares needed to repair the FPGA logic components with multiple faults.

Index terms — digital system, system-on-a chip, system-inpackage, FPGA functional logic blocks.

I. Introduction

At present there are many scientific publications, which cover SoC/SiP testing, diagnosis and repair problems [1-16, 19-20]. The testing and repair problem for the digital system logic components has a special place, because repair of faulty logic blocks is technologically complicated problem. Existing solutions, which are proposed in published works, can be divided on the following groups:

Manuscript received June 9, 2009.

Vladimir Hahanov is with the Kharkov National University of

Radioelectronics, Ukraine, 61166, Kharkov, Lenin Prosp., 14, room 321 (corresponding author to provide phone: (057)7021326; fax:

(057)7021326; e-mail: hahanov@ kture.kharkov.ua).

Eugenia Litvinova is with the Kharkov National University of

Radioelectronics, Ukraine, 61166, Kharkov, Lenin Prosp., 14, room 378 (phone: (057)7021421; fax: (057)7021326; e-mail: kiu@

kture.kharkov.ua).

Wajeb Gharibi is with Kingdom of Saudi Arabia (e-mail: gharibiw2002@yahoo.com),

Olesya Guz is with the Donetsk Institute of Road Transport, Donetsk, Ukraine (e-mail: kiu@kture.kharkov.ua)

in [6,7]. In critically important applications the acceptable integration level for CLB replacement is about 1000 logic blocks.

The repair technologies for digital system logic, implemented on-chip FPGA, are based on existence or introduction of LUT redundancy after place and route procedure executing. Physical faults, which appear in the process of fabrication or operation, become apparent as logical or temporary failure and result in malfunction of a digital system. Faults are tied not only to the gates or LUT components but also to a specified location on a chip. The idea of digital system repairing comes to the removal of a fault element by means of repeated place and route executing after diagnosis. At that two repair technologies are possible: 1) Blockage of a defective area by means of development the control scripts for long time place and route procedure. But it is not always acceptable for real time digital systems. The approach is oriented on removal the defective areas of any multiplicity. Blockage of the defective areas by means of repeated place and route executing results in repair of a digital system. 2) Place and route executing for repairing of real time digital systems can result in disastrous effects. It is necessary the technological approach that allows repairing of the digital system functionality for milliseconds, required for reprogramming FPGA by new bitstream to remove defective areas from chip functionality. The approach is based on preliminary generation all possible bitstreams for blockage future defective areas by means of their logical relocation to the redundant nonfunctional chip area. The larger a spare area the less a number of bitstreams, which can be generated a priori. Concerning multiple faults, not covered by a spare area, it is necessary to segment a digital project by its decomposition on disjoin parts, which have their own Place and Route maps. In this case a digital system that has n spare segments for n distributed faults can be repaired. The total chip area consists of (n+m) equal parts.

The research objective is development of repair method for FPGA logic blocks on basis of use the redundant chip area.

Problems: 1) Development of an algebra-logical repair method for logic blocks of a digital system on basis of FPGA. 2) Development of a method for logic blocks matrix traversal to cover FPGA faulty components by spare tiles. 3) Analysis of practical results and future research.

RI, 2009, №2

II. Algebra-Logical Repair Method for FPGA Blocks

The exact repair method for FPGA logic blocks by means of spares is represented. It enables to obtain quasi-optimal solution of coverage problem for faulty cells set by minimum quantity of spares. The method focuses on the implementation of digital system-in-package functionality to the Infrastructure IP. The objective function is

minimization of FPGA spares St, needed for the repair of faulty blocks in the siP operation by means of synthesis the disjunctive normal form of fault coverage and subsequent selection of a minimum conjunctive term

(St,Sl,...,St,...,St ) e St that answers the constraints on v 1 2’ ’ i ’ ’ mt 7

the number of spares mt < p , which enter into the logical

product:

min( S* ]

mt<p, S = (S1 vS2 v...vS v...vSn); S* =

= {Si,S2,...Sj,...Sp}.

FPGA functionality model is represented by a matrix of logic blocks operating by rows and columns of the structure M = |Mij |. In the process of designing the matrix attached

to a spare, consisting of rows and columns, which can be readdressed in the process of structure reconfiguration, when faults are detected.

A model of determining the minimum number of spares (rows and columns), covering all detected faults in a matrix of FPGA logic blocks, comes to the following items:

M = |Mii|,Mij

Here the matrix coordinate is equal to 1 if modulo 2 sum of faultless behaviour for the block f and real test response give 1 value, which corresponds to the defect in a block. After FPGA testing and fixation all faulty blocks the construction of faults coverage table

Y = |Yjj|,i = 1,n;j = 1,m is performed. Here columns

correspond to a fault set (“1” coordinates), fixed in the matrix M ( |m| = m ), rows are numbers of columns and

rows of FPGA blocks matrix, which cover faults, indicated in columns:

Y = Y- Y-1 1tj,lij

operating by rows and columns, which contain faults, we can find an optimal solution in the form of fault coverage in the metrics of faulty rows and columns. Then the trivial reassignment procedure is carried out for faulty rows and

columns, which replaced by faultless FPGA spare components.

To improve the solving of coverage task one-dimensional vector, concatenated from two sequences C and R by power n = p + q, is used instead of two-dimensional metrics components:

X=C*R=(C1,C2,...Ci,...Cp)*(R1,R2,...Rj,...Rq) = (3)

„ . (3)

=Xc*Xr= (X1,X2,...Xi,...Xp,Xp+1,Xp+2,...Xp+j,...Xp+q).

At that there is one-to-one correspondence between elements of initial sets (C, R) and resultant vector X that is established in the first column of Y matrix. Transformation X = C* R is carried out for ease of consideration and subsequent construction the disjunctive normal form in the frame of uniformity in the variables, which form the Boolean function. If given procedure is not performed, a function will be defined by variables of two types, which consist rows and columns of a memory matrix.

Y = v Yqj){Ypj,Yqj}=1 = MXpj vXqj). (4)

Last expression shows that every column identifies two variants of fault coverage - rows and columns. So a column has only two coordinates, which have unit value, and numbers of logical products is equal to total quantity of faults m, detected in FPGA matrix.

w ■ ■ ■ ■ ■

Y = v (k1X1 лkJ2X2л...лkjlXi л...лkJnXn),kjl = {0,1}. (5)

The generalize DNF is represented here; a number of terms is equal to w = 2n , n - numbers of rows in the set (C,R) or quantity of variables X in the matrix Y. All possible solutions (fault coverages by spares) are written by

the set of row identifiers for a coverage table. If kij at Xi is equal to zero, Xi is changed to an insignificant variable.

RI, 2009, №2

dimensional row and column metrics that satisfies the constraints of the objective function on spare quantity.

Example 2.2. Fulfill the repair process for FPGA matrix to determine the minimum quantity of spares, covering all faults. The matrix with faults and spares, highlighted by black color [19,20], is shown in Fig. 1.

Fig. 1. FPGA with faults and spares

The matrix has a spare for diagnosis and repair of faulty cells that is two rows and five columns. According to item 1 of the model for determining the minimum quantity of spares, covering all detected faults of a memory matrix, a coverage table for 10 faults

F = (F2,2,F2,5,F2,8,F4,3,F5,5,F5,8,F7,2,F8,5,F9,3,F9,7)

and eleven rows is formed:

Xj/ /Fl,j F2,2 F2,5 F2.8 F4,3 F5,5 % ^7,2 F8,5 fj,3 f,7

С2 ^ X1 1 1

С3 ^ X2 1 1

С5 ^ X3 1 1 1

C7 ^ X4 1

C8 ^ X5 1 1

R2 ^ X6 1 1 1

R4 ^ X7 1

R5 ^ X8 1 1

R7 ^ X9 1

R8 ^ X10 1

R9 ^ X11 1 1

Power or the number of rows in the table is determined by concatenation of columns C and rows R, which are in the one-to-one correspondence with the vector of variables X:

C*R = (C2,C3,C5,C7,C8)*(R2,R4,R5,R7,Rs,R9) - (7) - X = (X1,X2,X3,X4,X5,X6,X7,X8,X9,X10,Xu).

Construction of CNF is performed by a coverage table by means of writing the terms for unit values of columns:

Y = (X vX6)(X3 vX6)(X5 vX6)(X2 vX7XX3 vX8) (8) (X5 vX8)(X1 vX9XX3 vX0XX2 vXu)(X4 vXn).

Getting of disjunctive normal form is based on the Boolean algebra identities, which allows performing the logical multiplication all ten multiplicands and the subsequent minimization of DNF terms by applying the

operator ab v ab = a, absorption axioms and removing the same terms.

The final result is:

Y=X1X2X3X4X5 vX2X3X4X5X6X9 vX1X2X3X4X6X8 v vX2X3X4X6X8X9 vX1X2X4X6X8X10 vX2X4X6X8X9XW v vX]X4X6X7X8X1,XnvX]X2X3X5XnvX2X3X5X6X9Xnv (9) vX1X2X3X6X8Xu vX2X3X6X8X9Xu vX1X2X6X8X1oXn v vX2X6X8X9X10X11 vX1X3X5X7X11 vX3X5X6X7X9X11 v vX1X3X6X7X8Xn vX3X6X7X8X9Xn vX]X6X7XgX10Xn v

vX6X7X8XgX10Xn.

The choice of minimum length terms with 5 variables in given case determines a set of minimal solutions:

Y=X1X2X3X4X5 v X1X2X3X5X11 v X1X3X5X7X11 (10)

Transformation of the function to the coverage that contains variables in the form of FPGA rows and columns enables to represent the terms as follows:

Y = С2СзС5С7С8 vC2C3C5C8R9 v C2C5C8R4R9. (11)

All minimum solutions satisfy the requirements on quantity of spares, determined by numbers:

< 5) (Rr

< 2).

The subsequent repair technology for faulty FPGA blocks is electrical reprogramming of an address decoder for FPGA column or row. Concerning FPGA shown in Fig. 1 the readdressing of columns with faulty logic blocks to spare columns is realized, for instance, in compliance with first term of (11) that defines the relation:

Faulty column 2 3 5 7 8

Spare column 11 12 13 14 15

The computational complexity of an algebra-logical repair method for solving of the coverage task [17,20] is determined by the following expression:

Q = 2^1 + |C + R| x 2lFl, (12)

where 2 & - costs related to the synthesis of DNF by means of logical multiplication two-component disjunctions, the number of which is equal to quantity of faulty blocks (the fault coordinate is determined by a row or column number);

|C + R| x 2^1 is upper limit of computational cost needed to minimize the DNF on limiting set of variables that is equal to total quantity of rows and columns |C + R|.

In the worst case, when the coordinates of all faulty blocks are not correlated by rows and columns (unique), for instance, diagonal faults, computational complexity of the matrix method becomes dependent on the number of faulty cells only, and its analytic form is transformed to the following expression:

= 2И +

+ |C + R| x 2^1 2 x |F x 2^1 = 2

|C + R| < 2x |F = lFl x (1 + 2 x |F|).

If to use the numbers of faults m instead of the power of a fault set the previous expression is represented in simpler form:

Q = 2m x (1 + 2 x m) = 2m(2m +1). (14)

RI, 2009, №2

According to the Functional Intellectual Property, an algebra-logical repair method for FPGA logic blocks on basis of solving the coverage task is implemented into a chip as one of Infrastructure IP components that is designed for support of FPGA blocks and SoC availability.

Iii. Galls Method for a Logic Block Matrix to Cover the Faulty FPGA Components by Spare Tiles

Topology of a chip is represented by the tile matrix M = |M;j |i = 1,p; j = 1,q scalable horizontal and vertical by

integers (p x q). Every tile Мц has n logic blocks. The

matrix has an arbitrary number of faults, equal to k. There

are less or equal n faulty logic blocks in every tile. An example of a tile matrix with faults is shown in Fig. 2. Here the dimension of tile n is equal to 3 and matrix dimension in the number of tiles by rows and columns is equal to 5.

□ □ □ □ □ □ □ □ □ □ □ □ □ □ □

□ n □ □ n □ □ □ □ □ D □ в □ в

□ □ □ D □ □ □ D □ □ □ □ □ □ □

□ □ n □ □ □ □ □ □ □ □ □ □ в □

□ □ □ □ n □ □ D □ □ □ n □ □ □

□ □ □ □ □ □ □ □ □ □ n □ □ □ □

□ n □ □ □ □ □ □ □ □ □ □ □ в □

□ □ □ □ в □ □ □ □ □ □ в □ □ □

□ □ n n □ □ □ □ □ □ □ □ □ в □

□ □ □ □ □ □ □ □ □ □ □ □ □ □ □

□ □ n □ □ □ □ □ □ □ □ в в □ □

□ □ □ □ □ □ □ □ □ D □ □ □ в □

□ D □ □ □ D □ □ □ □ □ □ □ □ □

□ □ □ n □ □ □ D □ D □ □ □ □ □

□ □ □ □ □ □ □ □ □ □ □ □ □ в □

The traversal method for a matrix of logic blocks is represented by the steps below. It is designed to repair the FPGA components and enables to get quasi-optimal coverage of all faulty blocks by minimum numbers of spare tiles.

i = 1,p/n;j = 1,q;

,i = 1,p;j = 1,q/n.

Here every n coordinates of a row (column) is replaced by one coordinate with value that is determined by fr (fc) function or of n coordinates.

[0 ^ (000);

[ 1 ^ (1XX) v (X1X) v (XX1),X = {0,1}.

Мс = fr(fc) =

For instance, a procedure for obtaining a row traversal matrix gives the result

Here each column is compressed in the two coordinates on the rules of logical operation or, because the tile parameter n is equal to 3 here and below.

similarly a procedure for obtaining a column traversal matrix gives the result

M = My =

The row coverage criterion faulty blocks is determined by the following expression:

Qr = £ i=i

H - L. +1 j=i

£ Mr. ^ tl

Here Hr (Li) - maximum (minimum) index of J-th

after (before)

coordinate for a row of the matrix

which there are only zero coordinates in a row. Actually Hir - Lri + 1 is the units spread interval in rows of the

which gives the sum of unit row coordinates.

Further reduced estimates for all rows are added, which is the criterion of row coverage for faulty blocks.

The column coverage criterion is the following:

Qc = £ j=1

Hc - Lc+ 1i=1 iJ

Here H‘?(Lc) - maximum (minimum) index of J-th

coordinate for a column of the matrix

after (before)

which there are only zero coordinates in a column. Actually Hc - Lc +1 is the units spread interval in columns of the

which gives the sum of unit column

coordinates. Further reduced estimates for all columns are

RI, 2009, №2

added, which is the criterion of column coverage for faulty blocks.

coverage of faulty logic blocks by spares by means of

comparing the values of the structurization criteria Qr,Qc for the rows and columns:

j Sr ^ Qr < Qc;

|Sc ^ Qr > Qc.

In the first case, the faulty blocks coverage strategy is realized by sequential traversal of all tile rows. The second one - the traversal of tile columns is done.

modified matrix

. Each matrix row is represented by

the binary vector Mr = (М^М^^М-р.^М^) . Step 1.

Nulling of a zero coordinate counter and a spare tile counter: j = 0, Q = 0 . Step 2. Sequential scanning of the

vector elements j = j +1 ^ Mr = 0 up to the first “ 1

encountered M?j = 1 ^ (Q = Q +1, j = j + n -1) . From this

“1” it is counted n tiles, which are covered by the spare tile. The number of spare tiles Q is increased by 1. Step 3. If the condition j > q is true - the end of row processing.

Otherwise - go to step 2. The procedure is applied to all

rows of the modified matrix

Mr- ( MC

), resulting in

counter Q will contain the minimum number of spares to cover all faulty blocks. Similarly the tile traversal strategy

by columns (

) is performed. In this case the index i is

changed instead of j in a traversal procedure.

Example. For FPGA, shown in Fig. 2, according to item 2 of the repair model the construction of two matrixes is performed:

Mr = Mrj

MC = M.. = C ij

Further, in accordance with paragraph 3, the calculation of the structurization criteria is performed for the matrix above:

p/n 1 Д r 7 6 8 6 7

Qr = у — у Mr + + + +

i=1 Hr _ i - Lr i 1 il +1j=1 _ 14 12 13 12 13

Qc q/n 1 P c 6 7 7 7 7

= у —УМ + + + +

j=1 Hc j - Lc j л ^ il +1i=1 J 12 13 14 13 14

■ = 2,58.

As it can be seen from the above-mentioned criteria, the number of faulty coordinates in the columns reduced to the unit matrix is less than in the rows. Therefore, subject to item 4, the strategy for solving the coverage problem by column traversal is chosen: Sc ^ (Qr = 2,64 > Qc = 2,58).

Structural appeal of columns higher then rows, because the number of faults reduced to the matrix less than in the first case.

This strategy gives the actual quality of coverage - the number of faulty logic blocks of the matrix (by one spare tile), reduced to the necessary quantity of spares that is equal to:

Qc = —У F = 36/20 = 1,8.

For comparison - the row traversal procedure gives a lower quality:

Qr =—У F = 36/21 = 1,71.

The final coverage of a fault set has one tile more (21) than the solution obtained by the first method (20). So, the choice of coverage strategy on the basis of calculation and comparison the criteria for counting the number of unit coordinates, reduced to the actual unit matrix, confirms their consistency and the subsequent optimality of obtained coverage.

Fig. 3 shows statistics of the processing of different types logic block matrixes with faulty components. It demonstrates correctness of applying the proposed criterion, which shows the optimal and efficient strategy of matrix traversal to obtain minimum coverage of faulty logic blocks by spare tiles in all cases except the last one. In the latest variant the structurization criteria by rows greater than by

RI, 2009, №2

columns Qr = 1,78 > Qc = 1,55 that is the basis of covering

the faults by columns. In this case the coverage quality is *

Qc = 1,125 that corresponds to 16 spare tiles needed to repair all 18 faulty blocks. While the optimal solution is traversal of the matrix by columns, where the coverage *

quality is Qc = 1,2 that corresponds to 15 spare tiles only.

Fig. 3. Structurization criteria and coverage quality for the examples

IV. Software “aGalls” for Covering of Faulty FPGA Components by Spare Tiles

Software «aGalls» is designed for covering of faulty FPGA components by spare tiles by using the traversal method for logic block matrix.

The initial information is represented by a matrix of tiles

M = |Mjj|i = 1, p; j = 1,q, the dimension p x q, where each

tile has n*n logic blocks. The initial quantity of faults k is made to the matrix. The software detects the coordinates of all faults, constructs the binary coverage matrixes for faulty blocks by means of traversal the tiles by columns and rows, and calculates the quality criteria of fault coverage (Fig. 4).

Fig. 4. Calculation results

The program provides the opportunity to review the changes of temporary matrixes after covering the faulty blocks both horizontally and vertically. In addition, the actual number of spare tiles needed to cover all faults is displayed; it enables to estimate the correctness of the selected solution on the basis of calculating the criteria (Fig.

An algorithm for solving the coverage problem implemented in the software is represented below and in Fig. 6.

Fig. 6. Model of solving the optimal coverage task

RI, 2009, №2

j = j +1 ^ Mjj = 0 up to the first “1 ’

Mf = 1 ^ (Q = Q +1, j = j + n -1) by rows.

To check the validity of the criteria 200 experiments for the matrix M was carried out; the dimension of matrix is p*q, the number of blocks in the tile is n horizontally and vertically, and the number of faults is k, where

p = 3,7; n = 2,5; q = 3,7; k = 3,(n x p x q).

As a result, by using the criteria the most efficient way to repair has not been determined in 29% of cases, respectively a positive result - 71%. Fig. 7 presents diagrams showing the values of structurization criteria and coverage quality at the traversal of the modified matrix by rows and columns for the 10 examples. The dimension of the matrix was constant: 4 tiles in the horizontal and 5 ones vertical, the dimension of the tiles was 3*3 blocks.

Fig. 7. Structurization criteria and coverage quality

The software is used to verify and test the method for obtaining the quasioptimal fault coverage by minimum quantity of spare tiles. It can be implemented into a chip as embedded Infrastructure IP component, where the initial information about the topology of a chip has to be memorized during Place and Route process.

V. Conclusion

Algebra-logical repair method for FPGA logic blocks on the basis of solving the coverage task is focused on the implementation into a chip as one of Infrastructure IP components. It is designed to repair the FPGA blocks and SiP as a whole.

The method enables to obtain exact and optimal solution associated with the minimum number of spare blocks

needed to repair the FPGA logic components with multiple faults.

The traversal method for a logic block matrix is designed to repair the FPGA components by obtainment the solution in the form of quasioptimal coverage for all faulty blocks by minimum number of spare tiles. A choice one of two traversal strategies for rows or columns of a logic block matrix on the basis of the structurization criteria, which determine a number of faulty blocks, reduced to the unit modified matrix of rows or columns.

The technological solutions represented in the survey and proposed methods for diagnosis and repairing of digital system-on-a-chip and system-in-package correlates well with the analytical market research of electronics in 2009 and is formulated in the form of Gartner&s Top 10 Strategic Technologies for 2009: 1) Virtualization. 2) Cloud Computing. 3) Servers - Beyond Blades. 4) Web-Oriented Architectures. 5) Enterprise Mashups. 6) Specialized Systems. 7) Social Software and Social Networking. 8) Unified Communications. 9) Business Intelligence. 10) Green IT [http://www.gartner.com/].

As well as Gartner&s Top 10 correlates well with the analytical research of Computer Sciences Corporation (CSC), represented as 7 tendencies: 1) New media. Internet has become a full-fledged framework for creating and using audio, video and text content in a planetary scale. 2) Social software. Social networks attract millions of users, using the common interests. 3) Enhanced Reality. Gradually, but persistently it enters our lives. Virtual reality, where images of the users travel through the virtual worlds, it becomes practical in finding suitable products, services, products without their prior purchase. 4) Transparency of information. It will let you see yourself and the world with a given degree of detail by means of sensors and internet-cameras placed in the office, and throughout the world. The other side of the coin is how to hide and preserve personal space. 5) Wireless innovations. They allow running any application on any device, anywhere in the world. Here we should expect the appearance of conflict related to the division of frequencies between telecommunications operators, radio and television, cable and satellite companies, Internet service providers. It is expected the integrated solution of the problem on the basis of wireless technologies with mobile Internet-services. 6) New hardware and software platforms. Level of virtualization is increased. The number of applications which function on the same computer under different operating systems is growing exponentially. «Cloud computations», when a consumer pays for the use of computer infrastructure and applications to providers, stored client data on your own servers, significantly alter the entire calculation structure. Prospects of nanotechnology б molecular, quantum and optical computing become more realistic. Instead of silicon chips lighter and smaller elements: the atoms, DNA, spins of electrons and light will work. 7) Intelligent world. Semantic and networking technologies allow computing

RI, 2009, №2

devices to interpret the information on the algorithms of natural intelligence, whether text, voice, image, or life situations. Computers will be to teach, give advices, make predictions based on information received from the environment and the individual person. Self-learning semantic retrieval applications is developed in the Internet. A truly intelligent world is made, where people and computers will be able to talk and communicate with each other based on a combination of semantic and network technologies. This will result in the appearance of artificial intelligence, and possibly hyperintelligence, reading human thoughts [http://www.pcweek.ru/].

References

[1] Kwang-Ting (Tim) Cheng. The Need for a SiP Design and Test Infrastructure // IEEE Design and Test of Computers.- May-June, 2006.- P. 181.

[2] Fontanelli A. System-in-Package Technology: Opportunities and Challenges // Quality Electronic Design, 2008.- ISQED 2008, 9th International Symposium.- March, 2008.- P. 589 - 593.

[3] Appello D., Bernardi P., Grosso M., Reorda M.S. System-in-package testing: problems and solutions // IEEE Design Test of Computers.- Vol. 23, Issue 3.- May-June, 2006.- P. 203 - 211.

[4] Subhasish M.; Huang W.-J., Saxena N.R., Yu S.-Y., McCluskey E.J. Reconfigurable architecture for autonomous self-repair // IEEE Design Test of Computers.- Volume 21, Issue 3.- May-June, 2004.- P. 228-240.

[5] Ross R., Hall R. A FPGA Simulation Using Asexual Genetic Algorithms for Integrated Self-Repair // Adaptive Hardware and Systems, 2006.- AHS 2006.- First NASA/ESA Conference on Volume.- Issue 15-18 June 2006.- P. 301 - 304.

[6] Habermann S., Kothe R., Vierhaus H.T. Built-in self repair by reconfiguration of FPGAs // Proceedings of the 12th IEEE International Symposium on On-Line Testing.- 2006.- P. 187-188.

[7] S. Pontarelli, M. Ottavi, V. Vankamamidi, A. Salsano, F. Lombardi. Reliability Evaluation of Repairable/Reconfigurable FPGAs // 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06) .- October, 2006.- P. 227-235.

[8] Koal T., Vierhaus H. T. Basic Architecture for Logic Self Repair // 14th IEEE International On-Line Testing Symposium.- 2008.- P. 177-178.

[9] Kothe R., Vierhaus H.T., Coym T., Vermeiren W., Straube B. Embedded Self Repair by Transistor and Gate Level Reconfiguration // IEEE Design and Diagnostics of Electronic Circuits and Systems.-2006.- P. 208-213.

[10] Mange D., Sipper M., Stauffer A., Tempesti G. Toward self-repairing and self-replicating hardware: the Embryonics approach // Evolvable Hardware, Proceedings of the Second NASA/DoD Workshop.-2000.- P. 205-214.

[11] Miclea L., Szilard E., Benso A. Intelligent agents and BIST/BISR -working together in distributed systems // Proceedings of the Test Conference.- 2002.- P. 940-946.

[12] Rashad S. Oreifej, Carthik A. Sharma, Ronald F. DeMara. Expediting GA-Based Evolution Using Group Testing Techniques for Reconfigurable Hardware // Reconfigurable Computing and FPGA’s, 2006. ReConFig 2006. IEEE International Conference.- Sept., 2006.- P. 1-8.

[13] Anand D., Cowan B., Farnsworth O., Jakobsen P., Oakland S., Ouellette M.R., Wheater D.L. An on-chip self-repair calculation and fusing methodology // IEEE Design Test of Computers.- Volume 20, Issue 5.- Sept.-Oct., 2003.- P. 67-75.

[14] Wang S.-J., Tsai T.-M. Test and diagnosis of faulty logic blocks in FPGAs // IEEE Proceedings Computers and Digital Techniques.-Vol. 146, Issue 2.- March, 1999.- P.100 - 106.

[15] Pontarelli S., Cardarilli G.C., Malvoni A,. Ottavi M., Re M., Salsano A. System-on-chip oriented faulttolerant sequential systems implementation methodology // IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.- Oct., 2001.- P. 455 -460.

[16] Peter Rickert, William Krenik. Cell Phone Integration: SiP, SoC, and PoP // IEEE Design and Test of Computers.- May-June, 2006.- P. 188-195.

[17] Rossen K. Discrete Mathematics and its Applications, McGraw Hill, 2003. 824p.

[18] IEEE 1500 Web Site. http://grouper.ieee.org/groups/1500/.

[19] Hahanov V., Hahanova A., Chumachenko S., Galagan S. Diagnosis and repair method of SoC memory // WSEAS transactions on circuits and systems.- Vol.7.- 2008.- P. 698-707.

[20] Hahanov V., Obrizan V., Litvinova E., Ka Lok Man. Algebra-logical diagnosis model for SoC F-IP // WSEAS transactions on circuits and systems.- Vol. 7.- 2008.- P. 708-717.

RI, 2009, №2